Activities are aimed at design-for-test, test generation and selfrepair design:

• Low-overhead built-in selftest architectures for digital dataprocessing circuits
• Applications of design-for-testability methods to cores of system-on-chip
• Test generation for delay faults of systems-on-chip with simple chain wrapper architecture
• Test generation and fault simulation of asynchronous sequential circuits
• Online testing of digital circuits
• Built-in selftesting and selfrepair of memories
• Design of selfrepair architecture for logic cores with respect to low area overhead

Design of digital circuits

Activities are aimed at design, simulations and development:

• MDCT IP Core Generator with architectural model simulation
• Design and development of a FPGA to implement the algorithm for data encryption GOST
• Design and simulation of thealgorithm GOST with built-in self-test memory
• Design and simulation of the GOST core with JTAG architecture and P1500 standard
• Design and simulation of the encryption algorithm RIJNDAEL with implementation into FPGA – XILINX Spartan II
• Design of experimental board for testing digital designs (XILINX –Spartan II) with connection to an ISA PC bus
• Design and development of the data encryption circuit’s connection to an USB PC input
• Lab exercises for Mentor Graphics design kit with built-in self-test architecture applications to digital circuits